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Agilent HSDL-3202 IrDA(R) Data 1.3 Low Power Compliant 115.2 Kb/s Infrared Transceiver
Data Sheet
Description The HSDL-3202 is a new generation of low-cost Infrared (IR) transceiver modules from Agilent Technologies. It features one of the smallest footprints in the industry at 2.5 H x 8.0 W x 3.0 D mm. Although the supply voltage can range from 2.7 V to 3.6 V, the LED drive current is internally compensated to a constant 32 mA to guarantee link dis-
tance of IrDA Data 1.3 (low power) physical layer specification. The HSDL-3202 meets the link distance of 20 cm to other IrDA 1.3 low power devices, and 30 cm to standard one meter IrDA 1.3 devices. It is designed to interface to input/output logic circuits as low as 1.8 V.
Features * Ultra small surface mount package * Minimal height: 2.5 mm * VCC from 2.7 to 3.6 volts * Interface to input/output logic circuits as low as 1.8 V * LED supply voltage can range from 2.7 to 6 volts * Low ICC shutdown current - 10 nA typical * Complete shutdown - TxD, RxD, PIN diode * Three optional external components * Temperature performance guaranteed, -25C to 85C * 32 mA LED drive current * Integrated EMI shield * IEC825-1 class 1 eye safe * Edge detection input - prevents the LED from long turn on time Applications * Mobile telecom - cellular phones - pagers - smart phones * Data communication - PDAs - portable printers * Digital imaging - digital cameras - photo-imaging printers * Electronic wallet
CELL PHONES PAGERS PDAs CAMERAS
30
ILL
UM
I
NA
N TIO
CO
NE
.3 IrDA 1 OR ARD STAND WER O LOW P
.3 IrDA 1 R OWE LOW P
20 CM TO LOW POWER DEVICES 30 CM TO STANDARD DEVICES
CELL PHONES PAGERS PRINTERS PCs PDAs CAMERAS
Application Circuit
8 VLED
LED CURRENT SOURCE
C1 1.0 F
TXD
7 TXD
RXD SHUT DOWN
6 RXD 5 SD
SHIELD
Pinout, Rear View
4 AGND
3 C2 1.0 F C3 1.0 F 2
VCC I/O VCC
RX PULSE SHAPER
8
7
6
5
4
3
2
1
1 GND
I/O Pins Configuration Table Pin Symbol 1 2 3 4 5 6 7 GND IOVCC VCC AGND SD RXD TXD Description Ground Input/Output ASIC VCC Supply Voltage Analog Ground Shut Down Active High Receiver Data Output Active Low Transmitter Data Input Active High Notes Connect to system ground Connect to ASIC logic controller VCC voltage Regulated, 2.7 to 3.6 volts Connect to a "quiet" ground This pin must be driven either high or low. Do NOT float the pin. Output is a low pulse for 1.6 s when a light pulse is seen Logic High turns on the LED. If held high longer than ~ 20 s, the LED is turned off. TXD must be driven high or low. Do NOT float the pin. May be unregulated, 2.7 to 6 volts. Connect to system ground via a low inductance trace. For best performance, do not connect to GND or AGND directly at the part.
8 -
VLED SHIELD
LED Supply Voltage EMI Shield
Recommended Application Circuit Components Component C1 C2 C3 2 Recommended Value 1.0 F, 20%, Tantalum 1.0 F, 20%, Tantalum 1.0 F, 20%, Tantalum Note 1 1 1
Absolute Maximum Ratings For implementations where case-to-ambient thermal resistance is 50C/W. Parameter Storage Temperature Operating Temperature LED Supply Voltage Supply Voltage Input/Output Voltage Input Voltage: TXD, SD Output Voltage: RXD Solder Reflow Temperature Profile Transceiver I/O Truth Table The outputs (LED and RXD) are controlled by the combination of the TXD and SD (shutdown) pins and light falling on the receiver. As shown in the table below, the transmitter is non-inverting; the LED is on when the TXD pin is high and off when TXD is low. Symbol TS TA VVLED VCC IOVCC VI VO Min. -40 -25 0 0 0 0 -0.5 Max. 100 85 7 7 7 IOVCC + 0.5 IOVCC + 0.5 See page 12 Units C C V V V V V
Shutdown Mode Notes When the HSDL-3202 is in Shutdown Mode (SD pin high), the part presents different impedances to the rest of the circuit than when it is in normal mode. RXD Pin: This pin is NOT Tristate. During shutdown the equivalent circuit is a weak pullup (~300 k) to VCC. The ESD protection diodes to VCC and Ground are also present. TXD Pin: Input protection diodes are present. VLED Pin: Typical leakage current of 1.5 nA.
The receiver is inverting; the RXD pin is low during IrDA signal pulses and high when the receiver does not see any light. When shutdown (SD pin high), the LED is off (the state of the TXD pin does not matter), and the RXD pin is pulled high with a weak internal pullup. RXD Not valid Low High High 5 Notes 2 3, 4
SD Pin: Will draw approximately 10 nA when driven high.
SD Low
TXD High Low
LED On Off Off
Receiver Don't care IrDA signal No signal Don't care
High
Don't care
Caution: The BiCMOS inherent to this design of this component increases the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
3
Recommended Operating Conditions Parameter Operating Temperature Supply Voltage Input/Output Voltage LED Supply Voltage TXD, SD Input Voltage Receiver Input Irradiance Ambient Light Logic High Logic Low Logic High Logic Low Symbol TA VCC IOVCC VLED VIH VIL EIH EIL Min. -25 2.7 1.8 2.7 2/3 IOVCC 0 0.0081 2.4 Max. 85 3.6 VCC 6 IOVCC 1/3 IOVCC 500 0.4 115.2 Units C V V V V V mW/cm2 W/cm2 Kb/s IOVCC 1.8 V IOVCC 1.8 V For in-band signals For in-band signals 7 7 IOVCC operational at 1.5 V at reduced spec Conditions Notes
Receiver Data Rate
See Test Methods on page 15 for details
RXD Output Waveform
tPW VOH 90% 50% 10%
Receiver Wakeup Time Definition
SD
RX LIGHT
VOL
RXD tF tR tRW
VALID DATA
LED Optical Waveform
tPW LED ON 90% 50% 10% LED OFF
Transmitter Wakeup Time Definition
SD
TXD
tR
tF
TX LIGHT tTW
TXD "Stuck ON" Protection
TXD
LED
tOPW (MAX.)
4
Electrical & Optical Specifications Specifications hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range. All typical values are at 25C and 3.0 V unless otherwise noted. Parameter Receiver Viewing Angle Peak Sensitivity Wavelength RXD Output Voltage RXD Pulse Width RXD Rise Times RXD Fall Times Receiver Latency Time Receiver Wake Up Time Transmitter Radiant Intensity Viewing Angle Peak Wavelength Spectral Line Half Width Optical Pulse Width Optical Rise and Fall Times Optical Rise and Fall Times TXD Logic Levels High Low IEH 21/2 p 1/2 tOPW tOR tOF VIH VIL IH IL IVLED IVLED IVLED tTW 4 30 - - - - - - 2/3 IOVCC 0 - -1 - - - - 8 - 875 35 2.0 20 - - - - 0.01 -0.01 32 28.8 60 - - 2.23 30 600 600 mW/Sr TA = 25C, 1/2 15, TXD 2/3 IOVCC nm nm s s ns ns tPW (TXD) = 1.6 s TXD pin stuck high tPW (TXD) = 1.6 s tPW (TXD) = 1.6 s IOVCC 1.8 V IOVCC 1.8 V VI 2/3 IOVCC 0 VI 1/3 IOVCC VVLED = VCC = 3.6 V, VI(TXD) 2/3 IOVCC VVLED = VCC = 3.6 V, VI(TXD) 1/3 IOVCC VI(SD) 2/3 IOVCC 10 Logic High Logic Low 21/2 p VOH VOL tPW tR tF tL tRW 30 - - 880 - - IOVCC 0.3 3.5 70 50 50 100 nm V V s ns ns s s tPW (EI) = 1.6 s, CL = 9.0 pF Max. value @ IOVCC = 1.8 V tPW (EI) = 1.6 s, CL = 9.0 pF 8 9 IOH = -200 A, EI 0.3 W/cm2 IOL = 200 A Symbol Min. Typ. Max. Units Conditions Note
IOVCC - 0.2 - 0 - - - - - - 2.5 20 25 20 20
7 7
IOVCC V 1/3 IOVCC V 1 - 38 A A mA A A s
TXD Input Current High Low LED Current On Off Shutdown Transmitter Wake Up Time
0.0015 1 0.0015 1 12 100
5
Parameter Transceiver SD Logic Levels SD Input Current Supply Current High Low High Low Idle Peak Active Receive Peak Active Transmit IOVCC Current
Symbol Min. VIH VIL IH IL ICC2 ICC3
Typ.
Max.
Units
Conditions IOVCC 1.8 V IOVCC 1.8 V VI 2/3 IOVCC. Max value at 25C 0 VI 1/3 IOVCC. Max value at 25C VCC = 3.6 V, VSD = IOVCC VCC = 3.6 V, VI(TXD) 1/3 IOVCC, EI=0 VCC = 3.6 V, VI(TXD) 1/3 IOVCC
Note
2/3 IOVCC - 0 - - -300 - - - 10 -10 10 100 2.0
IOVCC V 1/3 IOVCC V 200 - 200 250 10.0 nA nA nA A mA
Shutdown ICC1
11, 12
ICC4
-
5.0
9.0
mA
VCC = 3.6 V, VI(TXD) 2/3 IOVCC
11
IIOVCC
-
30
200
nA
Notes: 1. C1,C2, and C3 must be placed within 0.7 cm of the HSDL-3202 to obtain optimum noise immunity. If VLED and VCC are tied together, then the application may use one less capacitor. 2. If TXD is stuck in the high state, the LED will turn off after about 20 s. 3. In-Band IrDA signals and data rates 115.2 Kb/s. 4. RXD Logic Low is a pulsed response. The condition is maintained for a duration that is dependent upon the data pattern. 5. RXD Logic High during shutdown is a weak pullup resistor (300 k). 6. An in-band optical signal is a pulse/sequence where the peak wavelength, p, is defined as 850 nm p 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification. 7. For in-band signals [115.2 Kb/s where 8.1 W/cm2 EI 500 mW/cm2]. 8. Latency is defined as the time from the last TXD light output pulse until the receiver has recovered full sensitivity. 9. Receiver wake up time is measured from the SD pin high-to-low transition or V CC power on to valid RXD output. 10. Transmitter wake up time is measured from the SD pin high-to-low transition or VCC power on to valid light output in response to a TXD pulse. 11. Typical values are at EI = 10 mW/cm 2. 12. Maximum value is at EI = 500 mW/cm 2.
6
Package Dimensions
MOUNTING CENTER
4.0 1.025
2.05 RECEIVER
C L EMITTER 2.2 1.175
2.5
2.85
1.05 1.25 2.55 4.0 8.0
0.35 0.65 0.80
3.0 1.85
2.9
C L UNIT: mm TOLERANCE: 0.2 mm
PIN 1 0.6 6.65 3.325
7
Moisture Proof Packaging The HDSL-3202 is shipped in moisture proof packaging. Once opened, moisture absorption begins. Recommended Storage Conditions Storage Temperature Relative Humidity 10C to 30C below 60% RH
Solder Pad, Mask and Metal Stencil
STENCIL APERTURE
METAL STENCIL FOR SOLDER PASTE PRINTING
LAND PATTERN
Time from Unsealing to Soldering After removal from the bag, the parts should be soldered within two days if stored at the recommended storage conditions. If times longer than two days are needed, the parts must be stored in a dry box. Baking If the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. Package In reels In bulk Temp. 60C 100C 125C 150C Time 48 hours 4 hours 2 hours 1 hour
SOLDER MASK PCB
Recommended Land Pattern
C L 1.35 SHIELD SOLDER PAD
MOUNTING CENTER
1.25 0.10
2.05
Baking should only be done once.
1.75
0.775
FIDUCIAL 0.60 0.475 1.425 UNIT: mm 2.375 3.325
8
Recommended Metal Solder Stencil Aperture It is recommended that only a 0.152 mm (0.006 inch) or a 0.127 mm (0.005 inch) thick stencil be used for solder paste printing. This is to ensure adequate printed solder paste volume and no shorting. See the table below the drawing for combinations of metal stencil aperture and metal stencil thickness that should be used. Aperture opening for shield pad is 2.7 mm x 1.25 mm as per land pattern.
APERTURES AS PER LAND DIMENSIONS
t
w l
Stencil Thickness, t (mm) Adjacent Land Keepout and Solder Mask Areas Adjacent land keepout is the maximum space occupied by the unit relative to the land pattern. There should be no other SMD components within this area. 0.2 mm is the minimum solder resist strip width required to avoid solder bridging adjacent pads. It is recommended that two fiducial crosses be placed at midlength of the pads for unit alignment. Note: Wet/Liquid PhotoImageable solder resist/mask is recommended.
SOLDER MASK
Aperture Size (mm) Length, l Width, w 2.60 0.05 3.00 0.05 0.55 0.05 0.55 0.05
0.152 mm 0.127 mm
8.2
0.2 2.6
3.0 UNITS: mm
9
PCB Layout Suggestion The following PCB layout shows a recommended layout that should result in good electrical and EMI performance. Things to note: 1. The ground plane should be continuous under the part, but should not extend under the shield trace.
Component Side
C3
2. The shield trace is a wide, lowinductance trace back to the system ground.
GROUND
C1
C2
SHUTDOWN
I/O VCC
GROUND
4. C1, C2, and C3 are optional supply filter capacitors; it may be left out if the supply is clean. 5. VLED can be connected to either unfiltered or unregulated power. If C1 is used, and if VLED is also connected to VCC, the connection should be before the C1 cap.
Circuit Side
10
SHIELD
3. The AGND pin is connected to the ground plane and not to the shield tab.
VLED
TXD
RXD
VCC
Pick and Place Misalignment Tolerance and Self-Alignment after Solder Reflow If the printed solder paste volume is adequate, the HSDL-3202 will self-align after solder reflow. Units should be properly reflowed in IR/hot air convection oven using the recommended reflow profile. The direction of board travel does not matter. Direction Definition
Tolerance for Rotational () Misalignment Mounted units should not be rotated more than 3 degrees with reference to center X-Y as shown in the direction definition. Units that are rotated more than 3 degrees will not self-align after solder reflow. Units with less than a 3 degree misalignment will self-align after solder reflow. Y-axis Misalignment of Castellation In the Y direction, the HSDL3202 does not self-align after solder reflow. Agilent recommends that the part be placed in line with the fiducial mark (midlength of land pad). This will enable sufficient land length (minimum of 1/2 land length) to form a good joint. See the drawing below.
Recommended Solder Paste/Cream Volume for Castellation Joints Based on calculation and experiment, the printed solder paste volume required per castellation pad is 0.22 cubic mm (based on either no-clean or aqueous solder cream types with typically 60% to 65% solid content by volume). Using the recommended stencil will result in this volume of solder paste.
Y X
Allowable Misalignment Direction X Y Tolerance 0.2 mm See text 3 degrees
EDGE
Tolerance for X-axis Alignment of Castellation Misalignment of castellation to the land pad should not exceed 0.2 mm or about one-half the width of the castellation during placement of the unit. The castellations will self-align to the pads during solder reflow.
MINIMUM 1/2 THE LENGTH OF THE LAND PAD FIDUCIAL
11
Reflow Profile
MAX. 245C R3 R4
230
T - TEMPERATURE - (C)
200 183 170 150 125 100 R1
R2
90 sec. MAX. ABOVE 183C
R5
50 25 0 P1 HEAT UP 50 100 150 200 P3 SOLDER REFLOW 250 P4 COOL DOWN 300
t-TIME (SECONDS) P2 SOLDER PASTE DRY
Process Zone Heat Up Solder Reflow Cool Down
Symbol T P1, R1 P3, R3 P3, R4 P4, R5 25C to 125C 125C to 170C 230C to 170C 170C to 25C
Maximum T/time 4C/s 0.5C/s -4C/s -3C/s
Solder Paste Dry P2, R2
170C to 230C (245C max.) 4C/s
The reflow profile is a straight line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different T/time temperature change rates. The T/time rates are detailed in the above table. The temperatures are measured at the component to printed-circuit board connections. In process zone P1, the PC board and HSDL-3202 castellation I/O pins are heated to a temperature of 125C to activate the flux in the solder paste. The temperature ramp-up rate, R1, is limited to 4C per second to allow for even heating of both the PC board and HSDL-3202 castellation I/O pins.
Process zone P2 should be of sufficient time duration (> 60 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 170C (338F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 230C (446F) for optimum results. The dwell time above the liquidus point of solder should be between 15 and 90 seconds. It usually takes about 15 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 90 seconds, the intermetallic growth within the solder connections becomes excessive, result-
ing in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 170C (338F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25C (77F) should not exceed -3C per second maximum. This limitation is necessary to allow the PC board and HSDL-3202 castellation I/O pins to change dimensions evenly, putting minimal stresses on the HSDL-3202 transceiver.
12
Window Design To ensure IrDA compliance, some constraints on the height and width of the window exist. The minimum dimensions ensure that the IrDA cone angles are met without vignetting. The maximum dimensions minimize the effects of stray light. The minimum size corresponds to a cone angle of 30 degrees, the maximum to a cone angle of 60 degrees. The drawing below shows the module positioned in front of a window.
Minimum and Maximum Window Sizes Dimensions are in mm. Depth (Z) 0 1 2 3 4 5 6 7 8 9 10 Y min. 1.70 2.23 2.77 3.31 3.84 4.38 4.91 5.45 5.99 6.52 7.06 X min. 6.80 7.33 7.87 8.41 8.94 9.48 10.01 10.55 11.09 11.62 12.16 Y max. 3.66 4.82 5.97 7.12 8.28 9.43 10.59 11.74 12.90 14.05 15.21 X max. 8.76 9.92 11.07 12.22 13.38 14.53 15.69 16.84 18.00 19.15 20.31
Window Height Y vs. Module Depth Z
Z
WINDOW HEIGHT Y - mm
16 14 12 10 8 6 4 2 ACCEPTABLE RANGE
Y
X
X is the width of the window, Y is the height of the window, and Z is the distance from the HSDL-3202 to the back of the window. The distance from the center of the LED lens to the center of the photodiode lens is 5.1 mm. The equations for the size of the window are as follows: X = 5.1 +2(Z + D) tan Y = 2(Z + D) tan Where is the required half angle for viewing. For the IrDA minimum, it is 15 degrees; for the IrDA maximum, it is 30 degrees. (D is the depth of the LED image inside the part, 3.17 mm). These equations result in the following tables and graphs:
0
0
2
4
6
8
10
MODULE DEPTH Z - mm
Window Width X vs. Module Depth Z
22 20
WINDOW WIDTH X - mm
18 16 14 12 10 8 6 0 2 4 6 8 10 ACCEPTABLE RANGE
MODULE DEPTH Z - mm
13
Flat Window Shape of the Window From an optics standpoint, the window should be flat. This ensures that the window will not alter either the radiation pattern of the LED, or the receive pattern of the photodiode. If the window must be curved for mechanical design reasons, place a curve on the back side of the window that has the same radius as the front side. While this will not completely eliminate the lens effect of the front curved surface, it will reduce the effects. The amount of change in the radiation pattern is dependent upon the material chosen for the window, the radius of the front and back curves, and the distance from the back surface to the transceiver. Once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. The following drawings show the effects of a curved window on the radiation pattern. In all cases, the center thickness of the window is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the transceiver to the back surface of the window is 3 mm. Curved Front, Flat Back (This option is not recommended and should not be used.)
Curved Front and Back (This option can be used if necessary for application purpose. A large radius of curvature is recommended and both front and back should have the same radius.)
14
Test Methods Background Light and Electromagnetic Field There are four ambient interference conditions in which the receiver is to operate correctly. The conditions are to be applied separately: 1. Electromagnetic Field: 3 V/m maximum (please refer to IEC 801-3, severity level 3 for details). 2. Sunlight: 10 kilolux maximum at the optical port. This is simulated with an IR source having a peak wavelength within the range of 850 nm to 900 nm and a spectral width of less than 50 nm biased to provide 490 W/cm2 (with no modulation) at the optical port. The light source faces the optical port. This simulates sunlight within the IrDA spectral range. The effect of longer wavelength radiation is covered by the incandescent condition. 3. Incandescent Lighting: 1000 lux maximum. This is produced with general service, tungsten-filament, gas-filled, inside frosted lamps in the 60 Watt to 100 Watt range to
generate 1000 lux over the horizontal surface on which the equipment under test rests. The light sources are above the test area. The source is expected to have a filament temperature in the 2700 to 3050 Kelvin range and a spectral peak in the 850 to 1050 nm range. 4. Fluorescent Lighting: 1000 lux maximum. This is simulated with an IR source having a peak wavelength within the range of 850 nm to 900 nm and a spectral width of less than 50 nm biased and modulated to provide an optical square wave signal (0 W/cm2 minimum and 0.3 W/cm2 peak amplitude with 10% to 90% rise and fall times less than or equal to 100 ns) over the horizontal surface on which the equipment under test rests. The light sources are above the test area. The frequency of the optical signal is swept over the frequency range from 20 kHz to 200 kHz. Due to the variety of fluorescent lamps and the range of IR emissions, this condition is not expected to cover all circumstances. It will provide a common floor for IrDA operation.
15
www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. March 21, 2001 Obsoletes 5980-1500E (5/00) 5988-2313EN

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